1. Field of the Invention
The present invention relates to a phase-locked loop circuit used for circuits operated in synchronization with each other, and more particularly to a phase-locked loop circuit in which a frequency of an oscillation clock signal in a lock state can be stably maintained even at an occurrence time of an abnormal condition such as the loss of a reference input signal.
2. Description of Related Art
FIG. 11 is a block diagram of a first conventional phase-locked loop circuit. In FIG. 11, 51 indicates a tank circuit. 52 indicates a phase comparing unit. 53 indicates a low pass filter (LPF). 54 indicates a voltage controlled crystal oscillator (VCXO). 55 indicates a frequency divider. An output signal of the VCXO 54 is fed back to the phase comparing unit 52 through the frequency divider 55 so as to make a frequency of output signal of the VCXO 54 agree with an input clock signal received in the tank circuit 51. Therefore, a conventional phase-locked loop (PLL) circuit is obtained.
Next, an operation of the first conventional phase-locked loop circuit will be described.
The tank circuit 51 is formed of a transformer, and an input clock signal is held in the tank circuit 51 for a predetermined time. Therefore, even though the input clock signal becomes unstable due to the occurrence of an abnormal condition in the input clock signal, a signal having a constant pulse width can be output from the tank circuit 51 for the predetermined time.
FIG. 12 is a block diagram of a second conventional phase-locked loop circuit. In FIG. 12, 61 indicates a phase comparing unit. 62 indicates a low pass filter (LPF). 63 indicates a voltage controlled crystal oscillator (VCXO) 64 indicates a frequency divider. 65 indicates an interruption detecting circuit for detecting the interruption of a reference clock signal. 66 indicates a control unit. 67 indicates a controlled voltage holding unit for holding and storing an output signal (denoting a controlled voltage for the VCXO 63) of the LPF 62. 68 indicates a selecting unit such as a selector.
In this conventional phase-locked loop circuit, a controlled voltage corresponding to a reference clock signal REF set in a normal condition is held and stored in the controlled voltage holding unit 67, and the interruption of the reference clock signal can be detected in the interruption detecting circuit 65. When the interruption of the reference clock signal is detected, the selection in the selecting unit 68 is changed by the control unit 66, and the controlled voltage held and stored in the controlled voltage holding unit 67 is selected in the selecting unit 68 and is output to the VCXO 63.
FIG. 13 is a block diagram of a third conventional phase-locked loop circuit disclosed in Published Unexamined Japanese Patent Application No. H7-273648 (1995). In FIG. 13, 71 indicates a phase comparing unit. 72 indicates a low pass filter (LPF). 73 indicates a voltage controlled oscillator (VCO). 74 indicates a counter for outputting a count value corresponding to a frequency division operation. 76 indicates a hold over circuit.
The configuration of the hold over circuit 76 is described. 77 indicates an interruption detecting unit. 78 indicates a control unit. 79 indicates a data holding unit. 80 indicates a comparing unit. 81 indicates a counter. 82 indicates a selecting unit. 83 indicates a pulse generating unit.
In the phase comparing unit 71, an error signal Sc indicating a phase difference between an input clock signal Sa and a feed-back signal Sb is produced. In the interruption detecting unit 77, the interruption of the input clock signal Sa is detected, and an interruption signal Sh is output. In the control unit 78, a control signal Si is output according to the interruption signal Sh and a signal Sl. In the data holding unit 79, the error signal Sc is held according to the control signal Si for a prescribed time, and a holding signal Sf denoting the error signal Sc is output. In the comparing unit 80, the error signal Sc and the holding signal Sf are compared with each other, a signal Sj is output in cases where the level of the error signal Sc is higher than that of the holding signal Sf, and the signal Sl is output in cases where the level of the error signal Sc is lower than that of the holding signal Sf. In the counter 81, a count value signal Sg indicating a count value is output according to the signal Sj and a signal Sk. In the selecting unit 82, a selection signal SQ indicating the selection of either the error signal Sc or the holding signal Sf is output according to the control signal Si. In the pulse generating unit 83, the feed-back signal Sb is output in an only case where a signal SB and the count value signal Sg are simultaneously set to a high level.
Next, an operation of the third conventional phase-locked loop circuit will be described below.
When the input clock signal Sa set in a normal condition is received in the phase comparing unit 71, the error signal Sc output from the phase comparing unit 71 is selected in the selecting unit 82, the error signal Sc is output from the selecting unit 82 as the selection signal SQ, the selection signal SQ is smoothed in the low pass filter 72, an oscillation clock signal Se is output from the voltage controlled oscillator 73, a count operation corresponding to a frequency division number is performed in the counter 74 according to the oscillation clock signal Se, and the signal SB is output from the counter 74. Thereafter, a pulse of the feed-back signal Sb is output from the pulse generating unit 83 to the phase comparing unit 71 each time the signal SB and the count value signal Sg simultaneously set to a high level are received in the pulse generating unit 83. Therefore, a phase-locked loop operation is performed in the third conventional phase-locked loop circuit.
When the interruption of the input clock signal Sa occurs due to the occurrence of an abnormal condition in the input clock signal Sa, the interruption of the input clock signal Sa is detected in the interruption detecting unit 77, and the interruption signal Sh is output from the interruption detecting unit 77 to the control signal Si. Thereafter, the control signal Si corresponding to the interruption of the input clock signal Sa is output from the control unit 78 to both the selecting unit 82 and the data holding unit 79. Because the error signal Sc obtained before the interruption of the input clock signal Sa is held in the data holding unit 79, the holding signal Sf denoting the error signal Sc obtained before the interruption of the input clock signal Sa is output from the data holding unit 79 to both the comparing unit 80 and the selecting unit 82 under control of the control signal Si. In the selecting unit 82, the holding signal Sf is selected under control of the control signal Si and is output as the selection signal SQ to the low pass filter 72. In the comparing unit 80, because the error signal Sc is interrupted, the error signal Sc cannot be received, but only the holding signal Sf is received. In this case, no signals Sj, Sk and Sl are generated in the comparing unit 80, an operation of the counter 81 is stopped, and the count value signal Sg keeps the count value obtained before the interruption of the input clock signal Sa. Therefore, the same feed-back signal Sb as that in the normal condition is output from the pulse generating unit 83 to the phase comparing unit 71.
However, in the first conventional phase-locked loop circuit shown in FIG. 11, because the tank circuit 51 has a coil of the transformer, an output condition in the tank circuit 51 is easily changed. Therefore, a problem has arisen that the first conventional phase-locked loop circuit is not stably operated due to the increase of jitters and wonders in an oscillation clock signal output from the voltage controlled crystal oscillator 54. Also, in cases where the interruption of the input clock signal Sa is continued for a long time, another problem has arisen that the first conventional phase-locked loop circuit cannot be adapted for the long time interruption.
Also, in the second conventional phase-locked loop circuit shown in FIG. 12, it is difficult to store a controlled voltage, which is set in a stable condition obtained before the occurrence of an abnormal condition, in the controlled voltage holding unit 67. Therefore, a problem has arisen that an abnormal controlled voltage is output from the controlled voltage holding unit 67 when an abnormal condition such as the interruption of the input clock signal occurs. Also, when a temperature is changed with the passage of time after the interruption of the reference clock signal REF, jitters and wonders are increased in an oscillation clock signal output from the voltage controlled crystal oscillator 63. Therefore, another problem has arisen that the second conventional phase-locked loop circuit is not stably operated due to the increase of jitters and wonders.
Also, in the third conventional phase-locked loop circuit shown in FIG. 13, the comparing operation of the phase comparing unit 71 is continued in a time period from the occurrence of an abnormal condition to the detection of the interruption of the input clock signal, the phase error signal Sc indicating a large phase difference is output from the phase comparing unit 71 in the time period. In this case, the voltage controlled oscillator (VCO) 73 is controlled by the phase error signal Sc, which is produced from the input clock signal Sa set in the abnormal condition and is output from the phase comparing unit 71, until the judgment that the abnormal condition occurs. Therefore, a problem has arisen that the frequency of the oscillation clock signal Se output from the voltage controlled oscillator 73 is considerably changed. Also, another problem has arisen that the phase error signal SC produced from the input clock signal Sa of the abnormal condition is erroneously stored in the data holding unit 79 until the judgment that the abnormal condition occurs.
In detail, there is little probability that the input clock signal Sa set in the normal condition is suddenly interrupted. FIG. 14 is a timing chart showing a phase change of the input clock signal Sa toward the interruption. The input clock signal Sa set in the normal condition is shown on the upper side, and the input clock signal Sa in a transfer time period from the normal condition to the abnormal condition is shown on the lower side. As shown in FIG. 14, when the input clock signal Sa is set in the abnormal condition, pulses of the input clock signal Sa having an abnormal frequency are output, the intermittent loss of the pulses is continued, no edges of the pulses are finally generated, and the interruption of the input clock signal Sa occurs.
In this case, as shown in FIG. 4 prepared for the explanation of the present invention later, even though an occurrence time T1 of the abnormal condition goes by, no interruption of the input clock signal Sa is detected in a time period in which pulses of the input clock signal Sa having an abnormal frequency are output and the intermittent loss of the pulses is continued, but the interruption of the input clock signal Sa is detected at a time T3 sufficiently elapsing after the generation of no edges of pulses of the input clock signal Sa.
An object of the present invention is to provide, with due consideration to the drawbacks of the conventional phase-locked loop circuit, a phase-locked loop circuit in which an oscillation clock signal having a frequency of an input clock signal set in a lock state is always output without changing a phase of the oscillation clock signal while suppressing wonders or jitters even though an abnormal condition such as the interruption of the input clock signal occurs.
The object is achieved by the provision of a phase-locked loop circuit including an abnormal condition detector for monitoring a pulse width of a phase error signal output from a phase comparator and judging an input clock signal to be in an abnormal condition in a case where the pulse width of the phase error signal exceeds a prescribed threshold value, a phase difference storage for storing the phase error signal output from the phase comparator, a selector for selecting either the phase error signal output from the phase comparator or the phase error signal stored in the phase difference storage and outputting the selected phase error signal to the low pass filter, and a control unit for controlling the selector to select the phase error signal stored in the phase difference storage in a case where it is judged by the abnormal condition detector that the input clock signal is in an abnormal condition.
In the above configuration, when the pulse width of the phase error signal exceeds a prescribed threshold value, the phase error signal stored in the phase difference storage is immediately sent to the low pass filter and the voltage controlled oscillator. Accordingly, the frequency of the input clock signal in the phase lock state can be maintained, no change of a phase of the oscillation clock signal occurs, and jitters and wonders can be suppressed. In particular, even though the interruption of the input clock signal occurs, a considerable change of frequency in the oscillation clock signal can be prevented, and the reliability of the frequency in the phase-locked looped circuit can be improved.
It is preferred that sample data is extracted from the phase error signal by the phase difference storage in synchronization with a sampling clock signal, and the sampling clock signal is obtained from the voltage controlled oscillator.
Therefore, the phase lock-looped circuit can be obtained at a low cost.
It is also preferred that sample data is extracted from the phase error signal by the phase difference storage in synchronization with a sampling clock signal, and the sampling clock signal is obtained from an external oscillator.
Therefore, the sampling clock signal can be easily obtained.
It is also preferred that the phase-locked loop circuit further includes a calculator for consecutively extracting a prescribed number of pulses from the phase error signal output from the phase comparator in a case where it is judged by the abnormal condition detector that the input clock signal is in a normal condition and making the phase difference storage store a width of one pulse in a case where widths of the pulses of the phase error signal agree with each other.
Therefore, the phase error signal in the abnormal condition is not stored in the phase difference storage, but the phase error signal in the normal condition can be stored in the phase difference storage.
It is also preferred that the phase-locked loop circuit further includes a calculator for extracting a prescribed number of pulses from the phase error signal output from the phase comparator in a case where it is judged by the abnormal condition detector that the input clock signal is in a normal condition, performing a calculation operation for widths of the pulses of the phase error signal and making the phase difference storage store an average of the widths of the pulses of the phase error signal.
Therefore, even though the phase of the input clock signal is changed, the oscillation clock signal having a stable phase can be obtained from the average stored in the phase difference storage.
It is also preferred that the average of the widths is calculated in the calculator each time a prescribed number of pulses are extracted from the phase error signal in a time period, each pair of time periods corresponding to two averages consecutively calculated overlap with each other, and one average stored in the phase difference storage as the phase error signal is replaced with the other average most recently calculated among the averages. Therefore, even though the phase of the input clock signal is changed with time, the oscillation clock signal having a stable phase can be obtained from the average most recently calculated in the calculator and stored in the phase difference storage.
It is also preferred that the average of the widths is calculated in the calculator each time a prescribed number of pulses are extracted from the phase error signal in a time period, each pair of time periods corresponding to two averages consecutively calculated overlap with each other, and one average stored in the phase difference storage as the phase error signal is replaced with another average of a prescribed number of averages consecutively calculated in a case where the averages agree with each other.
Therefore, the average stored in the phase difference storage can be replaced with the average having the higher reliability, the oscillation clock signal having a stable phase can be obtained even though the phase of the input clock signal is changed with time.
It is also preferred that the average of the widths is calculated in the calculator each time a prescribed number of pulses are extracted from the phase error signal in a time period, each pair of time periods corresponding to two averages do not overlap with each other, and one average stored in the phase difference storage as the phase error signal is replaced with the other average most recently calculated among the averages.
Therefore, even though the phase of the input clock signal is changed, the average stored in the phase difference storage can be renewed, and the oscillation clock signal having a stable phase can be obtained.
It is also preferred that the average of the widths is calculated in the calculator each time a prescribed number of pulses are extracted from the phase error signal in a time period, each pair of time periods corresponding to two averages do not overlap with each other, and one average stored in the phase difference storage as the phase error signal is replaced with another average of a prescribed number of averages consecutively calculated in a case where the averages agree with each other.
Therefore, the average stored in the phase difference storage can be replaced with the average having the higher reliability, the oscillation clock signal having a stable phase can be obtained even though the phase of the input clock signal is changed with time.
It is also preferred that the feed-back signal is loaded by the frequency divider according to an edge of the input clock signal, in a case where it is judged by the abnormal condition detector that the input clock signal is in the abnormal condition, to make a phase of the feed-back signal approach to that of the input clock signal.
Therefore, the phase of the feed-back signal can approach to that of the input clock signal in a simple configuration of the phase-locked loop circuit.
It is also preferred that a load point is determined by the frequency divider according to an edge of the input clock signal in a case where it is judged by the abnormal condition detector that the input clock signal is in the abnormal condition, and the feed-back signal is loaded with a value of the phase error signal stored in the phase difference storage at the load point by the frequency divider to make a phase of the feed-back signal approach to that of the input clock signal.
Therefore, the loaded feed-back signal can be output in a simple configuration of the phase-locked loop circuit on condition that a phase difference between the input clock signal and the loaded feed-back signal agrees with a phase difference of the phase error signal stored in the phase difference storage.